VLSI Projects      Contact : 97893 - 39435 , 95005 - 80005,96298 - 68306

Code No. Project Title Base Paper Abstract Video
VL33 A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems (IEEE 2016) Download Download
VL34 A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications(IEEE 2016) Download Download
VL35 A VLSI Circuit Emulation of Chemical Synaptic Transmission Dynamics and Postsynaptic DNA Transcription (IEEE 2016) Download Download
VL36 Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach (IEEE 2016) Download Download
VL37 Design Methodology for Voltage-Scaled Clock Distribution Networks(IEEE 2016) Download Download
VL38 Detector for MLC NAND Flash Memory Using Neighbor-A-Priori Information(IEEE 2016) Download Download
VL39 Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories (IEEE 2016) Download Download
VL40 Fault Tolerant Parallel Filters Based on Error Correction Codes (IEEE 2016) Download Download
VL41 Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation Application to Extraction of Best 10-nm Fin FET Parameter Values(IEEE 2016) Download Download
VL42 Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits (IEEE 2016) Download Download
VL43 Utilization-Aware Self-Tuning Design for TLC Flash Storage Devices (IEEE 2016) Download Download
VL44 A Modified Partial Product Generator for Redundant Binary Multipliers (IEEE 2016) Download Download
VL45 A New Paradigm of Common Sub expression Elimination by Unification of Addition and Subtraction(IEEE 2016) Download Download
VL46 Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation (IEEE 2016) Download Download
VL47 High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)(IEEE 2016) Download Download
VL48 A Scalable Approximate DCT Architectures for Efficient HEVC Compliant Video Coding (IEEE 2016) Download Download
VL49 Design for Testability of Sleep Convention Logic (IEEE 2016) Download Download
VL50 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation (IEEE 2016) Download Download
VL51 A Low-Cost Low-Power Ring Oscillator-based Truly Random Number Generator for Encryption on Smart Cards (IEEE 2016) Download Download
VL52 A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n- 1, 2n, 2n+ 1} (IEEE 2016) Download Download
VL53 A 116-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator (IEEE 2016) Download Download
VL54 Multiplier less Unity-Gain SDF FFTs(IEEE 2016) Download Download
VL55 A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic (IEEE 2016) Download Download
VL56 Low-Power Variation-Tolerant Nonvolatile Lookup Table Design (IEEE 2016) Download Download
VL57 Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkil (IEEE 2016) Download Download
VL58 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications (IEEE 2016) Download Download
VL59 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding (IEEE 2016) Download Download
VL60 High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations(IEEE 2016) Download Download
VL61 Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling (IEEE 2016) Download Download
VL62 A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate (IEEE 2015) Download Download
VL63 A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Application (IEEE 2015) Download Download
VL64 A New Gate for Low Cost Design of All-optical Reversible Logic Circuit (IEEE 2015) Download Download
VL65 A Novel Design of Reversible 2 4 Decoder (IEEE 2015) Download Download
VL66 A Novel Realization of Reversible LFSR for its Application in Cryptography (IEEE 2015) Download Download
VL67 A Novel Ternary Content Addressable Memory (TCAM) Design Using Reversible Logic(IEEE 2015) Download Download
VL68 A Single Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell(IEEE 2015) Download Download
VL69 Aging Aware Reliable Multiplier Design With Adaptive Hold Logic(IEEE 2015) Download Download
VL70 All Optical Implementation of MachZehnder Interferometer based Reversible Sequential Counters(IEEE 2015) Download Download
VL71 An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC(IEEE 2015) Download Download
VL72 Berger Check and Fault Tolerant Reversible Arithmetic Component Design(IEEE 2015) Download Download
VL73 Design Study of a Low Power High Speed Full Adder Using GDI Multiplexer(IEEE 2015) Download Download
VL74 Design and Analysis of Approximate Compressors for Multiplication(IEEE 2015) Download Download
VL75 Design And Development of Efficient Reversible Floating Point Arithmetic unit(IEEE 2015) Download Download
VL76 Design and Implementation of Arithmetic Logic Unit (ALU) Using Modified NovelBit Adder in QCA(IEEE 2015) Download Download
VL77 Design and Implementation of Field Programmable Gate Array Based Error Tolerant Adder for Image Processing Application(IEEE 2015) Download Download
VL78 Design of a Compact Reversible Carry Look Ahead Adder Using Dynamic Programming(IEEE 2015) Download Download
VL79 Design of a Power Optimal Reversible FIR Filter for Speech Signal Processing(IEEE 2015) Download Download
VL80 Design of Adiabatic Dynamic Differential Logic for DPA Resistant Secure Integrated Circuits(IEEE 2015) Download Download
VL81 Design of Full Adder circuit using Double Gate MOSFET(IEEE 2015) Download Download
VL82 Design of Low Power and High Speed Carry Select Adder using Brent Kung adder(IEEE 2015) Download Download
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